1. Field of the Invention
The present invention relates to the field of microprocessors and, more particularly, to bus architecture utilizing multiplexed address and data signals on a bus.
2. Prior Art
The use of a microprocessor and its associated bus architecture in a computer system is well known. Also well known is the coupling of peripheral components onto a bus for providing various other functions related to the computer system. Some examples of such devices are disk drives, disk drive controllers, graphics accelerators, audio cards, modems and network connections. Generally, these peripheral components are coupled to a bus for effecting data transfer between various components. Typically, with simpler computer systems, the data transfer is between the peripheral device and either the processor (CPU) or main memory.
In order to achieve the above described data transfer, a variety of bus architectures and protocols have been developed over time. One well known prior art standard is the ISA/EISA input/output (I/O) bus standard for writing/retrieving data to/from peripheral units. However, as technology evolves, these bus standards become inadequate or obsolete, due to additional constraints placed on them. A recent introduction of an improved bus standard, referred to as the Peripheral Component Interconnect (PCI), provides for a higher bandwidth and speed. The PCI standard is also flexible in that the bus architecture is independent of new processor technologies.
Additionally, another aspect of advancing technology in the computer system area, especially in regard to microprocessor based systems, is the evolution of hierarchical bus structures. With new computer systems it is possible that several levels of buses are provided, each bus delineating a functional area serviced by components coupled to it. In hierarchical bus systems, it is not rare to find buses having different bus standards. Thus, systems may incorporate both ISA/EISA and PCI buses, each servicing its own set of peripheral. Bridge units are then utilized to effect data transfer between the various buses.
Due to the requirement for faster speed, the PCI bus has received acceptance as one of the newer bus standards for use as a "local" bus in a microprocessor based computer system. The local bus couples the main peripheral units of the system to the processor. Essentially, the local bus is the hierarchical level below the host (CPU) bus. The PCI bus standard is well equipped to be used as such a local bus. Other buses, such as the ISN/EISA bus can be used at a level below the PCI local bus. In some instances, a second PCI bus may also be used as a lower level bus for grouping lower priority or lower speed peripherals.
The PCI bus specification requires a multiplexed address/data signal in which address signals are sent first on multiplexed bit lines, followed by the data. The PCI bus also permits both "writes" and "reads" to be originated by devices on the bus. Thus, not only will the processor issue write and read requests, the same requests can also be originated by the peripheral components on the bus. This also includes bridge units coupled to the PCI bus, which bridge units will permit writes and reads to be generated by whatever bus or component is coupled on the opposite side(s).
Although the speed of the PCI bus is quite rapid by today's standards, an inherent weakness is in the read request. Currently in a hierarchical bus system, if an agent at the top of the hierarchy issues a read from an agent at the bottom of the hierarchy, the read transaction will potentially incur several retries as it traverses the hierarchy. The retries occur as a result of writes that have been posted in the opposing direction of the read. These posted writes must be delivered to their destination before a read transaction, which may be returning status about the posted writes, can be allowed to complete. Since PCI bus agents are competing for the bridge resources from both directions, it can be seen that propagating a read transaction from one end of the hierarchy to another is a somewhat random process. Generally, the system requires the agent with the retried read transaction continue to repeat the read indefinitely, until the bridge that is fetching the data has returned with the data.
It is appreciated that an improvement to the PCI read transaction that would reduce or eliminate the number of retried reads will provide for a more efficient and potentially a faster bus architecture.